(a) Field of the Invention
The present invention relates to a bipolar transistor on a semiconductor-on-insulator substrate and, more particularly, to a structure of a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, on which a bipolar transistor is formed.
(b) Description of the Related Art
A SOI substrate is increasingly used for its advantages of a low power dissipation and a high speed operation of the resultant semiconductor device. FIGS. 1A to 1C show consecutive steps of a process for fabricating a bipolar transistor on a SOI substrate, which is described in Patent Publication JP-A-8-139180. First, an n.sup.+ -type polycrystalline silicon (polysilicon) layer 33 is grown on the bottom surface of an n-type single-crystalline silicon substrate 31, and a silicon oxide film 34 is formed thereon, followed by bonding a silicon supporting plate (substrate body) 32 onto the silicon oxide film 34 and polishing the top surface of the silicon substrate 31 to form a SOI substrate, as shown in FIG. 1A.
Subsequently, as shown in FIG. 1B, a plurality of separation grooves 35 are formed at the top surface of the silicon substrate 31 for exposing the top surface of the silicon oxide film 34, thereby separating the SOI substrate into a plurality of cell areas, followed by filling the separation grooves 35 with a silicon oxide film 36 to form separation channels. Then another groove (collector contact groove) 37 is formed in the silicon substrate 31 in each cell area, and the collector contact groove 37 is filled with a polysilicon film 38.
Subsequently, as shown in FIG. 1C, the polysilicon film 38 in the collector contact groove 37 is doped with phosphorous (P) by ion-implantation using a mask, followed by thermal diffusion thereof from the polysilicon film 38 to the polysilicon layer 33 to form an n.sup.+ -type collector contact region 38a and an n.sup.+ -type buried collector layer 33a. Thereafter, boron (B) is introduced to the silicon substrate 31 by selective ion-implantation to form a p-type base region 39, followed by introduction of arsenic (As) into a portion of the base region 39 to form an emitter region 40 in the base region 39. After forming a silicon oxide film 41 having openings on the emitter region 39 and the base region 40, a collector electrode 42, an emitter electrode 43 and a base electrode 44 are formed on the respective regions.
With the technique as described above, it is possible to reduce the horizontal distance between the collector and the base so as to reduce the dimensions of the bipolar transistor compared to a conventional technique wherein the collector contact region is formed by direct introduction of impurity ions from the surface of a silicon substrate without forming a groove to a depth reaching the buried contact layer which is formed beforehand in the cell area as one of a plurality of epitaxial layers.
In addition, since the polysilicon layer 33 is formed as underlying the silicon substrate 31 in the above technique, the buried collector layer 33a can be selectively formed as either p-type or n-type depending on the selection of the impurities after the SOI substrate is prepared. This means that the SOI substrate can be manufactured before the layout of the semiconductor device is designed, thereby reducing the turn-around-time (TAT) of the semiconductor device. Further, it has the advantage in that a plurality of epitaxial steps are not needed in the fabrication of the SOI substrate, which enables cost reduction in the fabrication process thereof.
In order to improve the frequency characteristics in a high-frequency range, it is generally requested to have a lower parasitic capacitance between the collector and the base of the bipolar transistor. In the structure fabricated by the process as described above, however, there is a problem in that the parasitic capacitance between the buried collector layer and the base region in the silicon substrate is relatively large.